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TS4985
2x1.2w Stereo Audio Power Amplifier with Dedicated Standby Pins
PRODUCT PREVIEW
s s s s s s s
Operating from VCC=2.2V to 5.5V 1.2W output power per channel @ VCC=5V, THD+N=1%, RL=8 10nA standby current 62dB PSRR @ 217Hz with Grounded inputs High SNR: 106dB(A) typ. Near Zero Pop & Click Lead-free 15 bumps flip-chip package
Pin Connections (top view)
Flip-Chip 15 bumps
Description
The TS4985 has been designed for top of the class stereo audio applications. Thanks to its compact and power dissipation efficient flip-chip package, it suits various applications. With a BTL configuration, this audio power amplifier is capable of delivering 1.2W per channel of continuous RMS Output Power into an 8 load @ 5V. Each output channel (Left and Right), has an external controlled standby mode pin (STDBYL&STDBYR) to reduce the supply current to less than 10nA per channel. The device also features an internal thermal shutdown protection. The gain of each channel can be configured by external gain setting resistors.
Pin Connection (top view)
VCC2
IN+R
VCC1
STDBYL
IN-R
VO+L VO-L BYPASS
VO+R VO-R
IN+L
GND2
Applications
s s s s Cellular mobile phones Notebook & PDA computers LCD monitors & TVs Portable audio devices
IN-L
STDBYR
GND1
Order Codes
Part Number TS4985EIJT 1 TS4985EIKJT 2
1) E = Lead-free Flip-Chip 2) K = Back coating option
Temperature Range -40, +85C
Package Flip-Chip
Packaging Tape & Reel
Marking
November 2004
Revision 1
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This is preliminary information on a new product now in development. Details are subject to change without notice.
TS4985 1 Application Diagram
Application Diagram
Figure 1 : Typical application schematics
Cfeed-L
Rfeed-L 22k
VCC
A5 VCC1 VCC2
B6
Input L GND
Cin-L 100n
VCC
Rin-L 22k
A1
IN-L
VO-L A3
B2
IN+L
+
1 2 3
C5 Standby L Bias AV = -1 C3
+
+
Cs 1u
Neg. Output L
VO+L
B4
Pos. Output L
Bypass
+
Cb 1u
D6
Cin-R Input R GND 100n 22k
IN+R
+ VO-R E3
Rin-R
E5
IN-R
-
VCC
AV = -1 C1 Standby R + VO+R D4
Neg. Output R Pos. Output R
1 2 3
GND1
GND2
TS4985 D2
E1
Cfeed-R
Rfeed-R 22k
Table 1: External Component Descriptions
Components RIN L,R CIN L,R RFEED L,R CS CB AV L, R Functional Description Inverting input resistors which sets the closed loop gain in conjunction with Rfeed. These resistors also form a high pass filter with CIN (fc = 1 / (2 x Pi x RIN x CIN)) Input coupling capacitors which blocks the DC voltage at the amplifier input terminal Feedback resistors which sets the closed loop gain in conjunction with RIN Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Closed loop gain in BTL configuration = 2 x (RFEED / RIN) on each channel
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Absolute Maximum Ratings 2 Absolute Maximum Ratings
TS4985
Table 2: Key parameters and their absolute maximum ratings
Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Supply voltage
2 1
Parameter
Value 6 GND to VCC -40 to + 85 -65 to +150 150 tba Internally Limited
Unit V V C C C C/W
Input Voltage Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient Power Dissipation Human Body Model Machine Model Latch-up Immunity
3
2 200 200mA
kV V
1) All voltages values are measured with respect to the ground pin. 2) The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V. 3) All Voltage values are measured from each pin with respect to supplies.
Table 3: Operating Conditions
Symbol VCC VICM VSTB RL ROUTGND TSD RTHJA
1)
Parameter Supply Voltage Common Mode Input Voltage Range Standby Voltage Input: Device ON Device OFF Load Resistor Resistor Output to GND (VSTB = GND) Thermal Shutdown Temperature Thermal Resistance Junction to Ambient Flip Chip1
Value 2.2 to 5.5 1.2V to VCC 1.35 VSTB VCC GND VSTB 0.4
Unit V V V
4 1
150 tba
M C C/W
When mounted on a 4-layer PCB.
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TS4985 3 Electrical Characteristics
Electrical Characteristics
Table 4: VCC = +5V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 1Wrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 65 15 1.5 0.9 Parameter Min. Typ. 7.4 10 Max. 12 1000 Unit mA nA mV W %
1 1.2 0.2
10
PSRR
55 55
62 64 tba tba 90 10 1.3 0.4 130
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz
M
GM GBP
1) Standby mode is activated when Vstdby is tied to Gnd. 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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Electrical Characteristics
Table 5: VCC = +3.3V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 400mWrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 Gain Bandwidth Product RL = 8 65 15 1.5 1.5 375 Parameter Min. Typ. 6.6 10 Max. 12 1000
TS4985
Unit mA nA mV mW %
1 500 0.1
10
PSRR
55 55
61 63 tba tba 110 10 1.2 0.4 140
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz MHz
M
GM GBP GBP
1) Standby mode is activated when Vstdby is tied to Gnd. 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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TS4985
Table 6: VCC = +2.6V, GND = 0V, Tamb = 25C (unless otherwise specified)
Symbol ICC ISTANDBY Voo Po THD + N Supply Current No input signal, no load Standby Current 1 No input signal, Vstdby = GND, RL = 8 Output Offset Voltage No input signal, RL = 8 Output Power THD = 1% Max, F = 1kHz, RL = 8 Total Harmonic Distortion + Noise Po = 200mWrms, Av = 2, 20Hz F 20kHz, RL = 8 Power Supply Rejection Ratio2 RL = 8, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8 F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1F) Standby Time (Cb = 1F) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8, CL = 500pF Gain Margin RL = 8, CL = 500pF Gain Bandwidth Product RL = 8 Parameter
Electrical Characteristics
Min.
Typ. 6.2 10
Max. 12 1000
Unit mA nA mV mW %
1 220 300 0.1
10
PSRR
55 55
60 62 tba tba 125 10 1.2 0.4 65 15 1.5 150
dB
Crosstalk TWU TSTDB VSTDBH VSTDBL
dB ms s V V Degrees dB MHz
M
GM GBP
1) Standby mode is activated when Vstdby is tied to Gnd. 2) All PSRR data limits are guaranteed by production sampling tests Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc.
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Package MechanicaL Data 4 Package MechanicaL Data
TS4985
4.1 TS4985EIJT Pinout and Package Mechanical Data
4.1.1 Pinout (top view)
4.1.2 Marking (top view)
E
6 5 4 3 2 1
IN-L VCC1
VCC2
IN+R
STDBYL
IN-R
VO+L VO-L BYPASS
VO+R VO-R
A85 YWW
IN+L
GND2
STDBYR
GND1
A
B
C
D
E
s Balls are underneath
s s s s s
ST Logo Part number: A85 Three digits Datecode: YWW E symbol for lead-free The dot is for marking pin A1
4.1.3 Package mechanical data for 15-bump flip-chip
2.40 mm
0.25m m 0.5mm
1.90 mm
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Die size: 2.40 x 1.90 mm 30m Die height (including bumps): 600m Back Coating height(optional): 100m Bump Diameter: 315m 50m Bump Diameter Before Reflow: 300m 10m Bump Height: 250m 40m Die Height: 350m 20m Pitch: 500m 50m Coplanarity: 60m max.
0.3mm 0.86mm
100 m Back coating
*
600 m
* Optional
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TS4985 4.1.4 Tape & reel specification (top view)
Package MechanicaL Data
4
1.5
1 A A
Die size Y + 70m
1
8
Die size X + 70m
4
All dimensions are in mm
User direction of feed
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Revision History 5 Revision History
Date 01 Nov 2004 Revision 1 First Release Description of Changes
TS4985
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved
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